With the trend towards mobile and network aware applications, more and more computational intensive applications are being implemented in low power embedded systems.

Hardware/Software Co-design approach is often employed to ensure an efficient implementation of these application. Given a computationally intensive algorithm, such as signal processing modules in the source code of a GPS receiver, the computationally intensive and time critical part of the algorithm are first identified. These modules are then implemented using hardware such as FPGA. The code which are non-time critical can remain as software, running on a processor. The interface between the hardware modules with the software is a critical part of the overall design. As a result of parallelized hardware, the bottleneck of the system is eliminated, and this would allow the system to run on a lower system clock speed, saving cost and power. Students taking on this project will have the chance to use the Xilinx EDK/ISE and Celoxica’s DK Suite to implement the GPS receiver on a FPGA board.

Early development on C to HDL was done by Ian Page and colleagues at Oxford University in the 90s. The aim is to code hardware circuit rapidly in a high level language that is easy to learn as compare to HDL which can be tedious and time consuming. Subsequenctly a number of vendors have attempted to create tools that convert C or C-like languages into a hardware description language like VHDL or Verilog. For instance, the Celoxica's DK4 design suit.

For any computationally intensive digital system design project, integrating a FPGA (Field-Programmable Gate Array) with
a micro-processor core can lead to increase performance,
while maintaining a high degree of flexibility in the system.
However, there is a need to perform rapid design exploration
in order to determine the benefits of mapping a piece of
software-code to the FPGA. Here rapid area-time estimation is an instrumental step for efficient design exploration of FPGA-based implementations.

Synthesizing the Design

During synthesis, the HDL files are translated into gates and optimized for the target architecture. User Constraint File (UCF) style syntax is used to define synthesis and timing
constraints. Such as the physical pin location for a particular Input output connection from FPGA internal signal to the outside world.

Translating the Design

During translation, the NGDBuild program performs the following functions:

• Converts input design netlists and writes results to a single merged NGD net merged netlist describes the logic in the design as well as any location and tim
constraints.
• Performs timing specification and logical design rule checks.
• Adds constraints from the User Constraints File (UCF) to the merged netlist.

Mapping

The design is mapped into CLBs and IOBs. Map performs the following functions:

• Allocates CLB and IOB resources for all basic logic elements in the design.
• Processes all location and timing constraints, performs target device optimizations, and runs a design rule check on the resulting mapped netlist.

Placing and Routing the Design

It is a stage in design which a layout of a larger block of the circuit or the whole circuit is created from layouts of smaller sub-blocks.

Placement : determining the positions of the sub-blocks in the design area

Routing: interconnecting the sub-blocks.

After the mapped design is evaluated, the design can be placed and routed. With timing driven PAR, the process is run with the timing constraints specified in the input netlist and/or in the constraints file. With non timing driven PAR, the procecss is run, ignoring all timing constraints.